Subscribers
3.6K
🔥 Buzz rank
#482 NEW
Total Views
682.8K
Videos
91
Est. monthly earnings
$19 – $37
How we estimate: ~7.6K recent monthly views × an estimated ad RPM of
$2.51–$4.83 per 1,000 views —
adjusted for Lifestyle (sociology) content.
Yearly ≈ $228 – $444.
Excludes sponsorships, memberships & merch. Full methodology →
Known for
108.1K views
IIT Guwahati Drone video || IIT Campus Tour
14K views
How to Write Spice code || Inverter Simulation using NGspice | Pspice | Spice Netlist
12.1K views
Cadence-12: Creating Symbol from schematic in Cadence || Virtuoso symbol creation
11.8K views
Cadence-19: EMX Inductor Design | On-Chip Inductor Design for high Q and L with freq | EM Simulation
About
Promoting VLSI Design culture by providing resources and fostering the development of innovative circuits and microsystems, focusing on design and demonstration.
Learn || Think || Design
For any query, contact - labee311@gmail.com
Learn || Think || Design
For any query, contact - labee311@gmail.com
💡 Did you know?
- Joined YouTube in 2017 — 8 years ago.
- Ranked #2,714 among all creators tracked on SocialDB.
- One of the top Lifestyle (sociology) creators — #532 in the niche.
- Averages 7.6K views per video.
- Posts about 0.2× per week.
- 3.52% engagement rate.
- Gained 10 subscribers in the last 7 days.
📸 Gallery
Performance
7.6K
Avg views / video
266
Avg likes
3
Avg comments
3.52%
Engagement rate
0.2
Uploads / week
7.5K
Lifetime avg / video
Engagement rate = (likes + comments) ÷ views across recent videos.
Recent videos
IIT Guwahati Campus Drone Video || Tour
2.5K views · 2 years ago
Analog IC Testing in IIT Guwahati Lab || RFIC Measurements using Probe Station
2.2K views · 3 years ago
Cadence-19: EMX Inductor Design | On-Chip Inductor Design for high Q and L with freq | EM Simulation
11.8K views · 3 years ago
Cadence-18: PEX of Layout using Calibre || Post Layout Simulation
8.6K views · 3 years ago
IIT Guwahati Drone video || IIT Campus Tour
108.1K views · 3 years ago
Cadence-17: LVS using Calibre || Layout vs Schematic (LVS) check || Cadence Layout debugging
5.6K views · 3 years ago
Cadence-16: DRC of Layout in Calibre | Design Rule Check (DRC) || Post Layout Simulation
5.5K views · 3 years ago
IIT Guwahati Campus Tour || Indian Institute of Technology |
5.3K views · 3 years ago
Cadence-15: Layout of MOS || fingers | Multipliers | RFMOS Layout || Post Layout Simulation
7.5K views · 3 years ago
Cadence-14: Basics of Layout Design and Debugging | Calibre Cadence Layout Rules 4 Error free design
4.8K views · 3 years ago
Spice Simulation using NGspice || Nodal and Mesh Analysis using spice l Basics of spice
692 views · 3 years ago
Cadence-13: Replace AnalogLib passives with TSMC library | Inductor from TSMC library | foundry PDK
2.9K views · 3 years ago
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